Determining Optimal Ion Implantation Conditions to Prevent Double Snapback in High-Voltage Electrostatic Protection DDDNMOS Devices
Keywords:
ESD (electrostatic discharge), DDDNMOS (double diffused drain N-type MOSFET), Double snapback, Vav (avalanche breakdown voltage), Design window, Simulation, DPS (double polarity source), ColligationAbstract
Process and device simulations were performed to determine the optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS (double diffused drain N-type MOSFET) device for electrostatic discharge (ESD) protection. By examining the effects of HP-Well, N- drift and N+ drain ion implantation on the double snapback and avalanche breakdown voltages, it was possible to prevent double snapback and improve the electrostatic protection performance. Optimizing the ion implantation concentration in the N- drift region rather than the HP-Well region prevents the transition from the primary on-state to the secondary on-state, leading to improved ESD protection performance. As the concentration of the N- drift region affects both leakage current and avalanche breakdown voltage, for process technologies operating with voltages exceeding 30 V, implementing
new structures like DPS or optimizing process conditions can result in improved ESD protection performance.
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